PCF85133USLASH2DASLASH1 datasheet(29/41 Pages) NXP

29 / 41 page

PCF85133_1

Product data sheet

Rev. 1 — 17 February 2009

29 of 41

NXP Semiconductors

PCF85133

Universal LCD driver for low multiplex rates

12. Application information

12.1 Cascaded operation

In large display conﬁgurations of up to sixteen PCF85133s can be recognized on the

same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the

programmable I2C-bus slave address (SA0).

When cascaded PCF85133s are synchronized, they can share the backplane signals

from one of the devices in the cascade. Such an arrangement is cost-effective in large

LCD applications since the backplane outputs of only one device need to be

through-plated to the backplane electrodes of the display. The other PCF85133s of the

cascade contribute additional segment outputs but their backplane outputs are left

open-circuit (see Figure 20).

For display sizes that are not multiple of 320 elements, a mixed cascaded system can be

considered containing only devices like PCF85133 and PCF8532. Depending on the

application, one must take care of the software commands compatibility and pin

connection compatibility.

In a cascade only one master but multiple slaves are allowed. No external clock should be

used; the slaves get the clock from the master.

The SYNC line is provided to maintain the correct synchronization between all cascaded

PCF85133s. This synchronization is guaranteed after the power-on reset. The only time

that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in

adverse electrical environments, or by the deﬁnition of a multiplex mode when

PCF85133s with different SA0 levels are cascaded).

Table 18.

Addressing cascaded PCF85133

Cluster

Bit SA0

Pin A2

Pin A1

Pin A0

Device

100000

0011

0102

0113

1004

1015

1106

1117

210008

0019

01010

01111

10012

10113

11014

11115

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