PCF85133USLASH2DASLASH1 datasheet(19/41 Pages) NXP

19 / 41 page

PCF85133_1

Product data sheet

Rev. 1 — 17 February 2009

19 of 41

NXP Semiconductors

PCF85133

Universal LCD driver for low multiplex rates

7.16.3 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during

which time the master generates an extra acknowledge related clock pulse.

• A slave receiver which is addressed must generate an acknowledge after the

reception of each byte.

• Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter.

• The device that acknowledges must pull-down the SDA line during the acknowledge

clock pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse (set-up and hold times must be taken into

consideration).

• A master receiver must signal an end of data to the transmitter by not generating an

acknowledge on the last byte that has been clocked out of the slave. In this event the

transmitter must leave the data line HIGH to enable the master to generate a STOP

condition.

Acknowledgement on the I2C-bus is shown in Figure 14.

7.16.4 I2C-bus controller

The PCF85133 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or

transmit data to an I2C-bus master receiver. The only data output from the PCF85133 are

the acknowledge signals from the selected devices. Device selection depends on the

I2C-bus slave address, on the transferred command data and on the hardware

subaddress.

In a single device application, the hardware subaddress inputs A0, A1 and A2 are

normally tied to VSS which deﬁnes the hardware subaddress 0. In multiple device

applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding

scheme such that no two devices with a common I2C-bus slave address have the same

hardware subaddress.

Fig 14. Acknowledgement on the I2C-bus

mbc602

START

condition

clock pulse for

acknowledgement

not acknowledge

acknowledge

data output

by transmitter

data output

by receiver

SCL from

master

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