PCF85133USLASH2DASLASH1 datasheet(17/41 Pages) NXP

17 / 41 page

PCF85133_1

Product data sheet

Rev. 1 — 17 February 2009

17 of 41

NXP Semiconductors

PCF85133

Universal LCD driver for low multiplex rates

An additional feature is for an arbitrary selection of LCD segments to blink. This applies to

the static and 1:2 multiplex drive modes and can be implemented without any

communication overheads. By means of the output bank selector, the displayed RAM

banks are exchanged with alternate RAM banks at the blink frequency. This mode can

also be speciﬁed by the blink-select command.

In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of

LCD segments can blink by selectively changing the display RAM data at ﬁxed time

intervals.

If the entire display can blink at a frequency other than the typical blink frequency. This

can be effectively performed by resetting and setting the display enable bit E at the

required rate using the mode-set command (see Table 10).

7.16 Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

By connecting pin SDAACK to pin SDA on the PCF85133, the SDA line becomes fully

I2C-bus compatible. Having the acknowledge output separated from the serial data line is

advantageous in Chip-On-Glass (COG) applications1. In COG applications where the

track resistance from the SDAACK pin to the system SDA line can be signiﬁcant, possibly

a voltage divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO)

track resistance. It is possible that during the acknowledge cycle the PCF85133 will not be

able to create a valid logic 0 level. By splitting the SDA input from the output the device

could be used in a mode that ignores the acknowledge bit. In COG applications where the

acknowledge cycle is required, it is necessary to minimize the track resistance from the

SDAACK pin to the system SDA line to guarantee a valid LOW level.

The following deﬁnition assumes SDA and SDAACK are connected and refers to the pair

as SDA.

Table 7.

Blink frequencies

Blink mode

Operating mode ratio

Blink frequency with respect to fclk (typical)

Unit

fclk = 1.970 kHz

fclk = 2.640 kHz

off

blinking off

2.5

3.5

1.3

1.7

0.6

0.9

clk

768

---------

clk

1536

------------

clk

3072

------------

For further information, please consider the NXP application note:

AN10170, Design guidelines for COG modules with NXP

monochrome LCD drivers.

PCF85133U/2DA/1 датащи(PDF) 17 Page - NXP Semiconductors

PCF85133U/2DA/1 датащи(HTML) 17 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

датащи скачать

ссылки URL