WM8141CFTSLASHV datasheet(27/31 Pages) WOLFSON

27 / 31 page

Production Data

WM8141

WOLFSON MICROELECTRONICS LTD

PD Rev 3.0 October 2000

MONOCHROME CCD

BUFFER

WM8141

INCLUDING

RECOMMENDED

EXTERNAL

COMPONENTS

DATA

CONTROL I/F

CLOCKS

OUT

RINP

See sensor

datasheet for

details

SENSOR TIMING

Maximum pixel rate = 1.5Mpixels/second (Mode 6)

Maximum pixel rate = 2Mpixels/second (Mode 2)

Maximum pixel rate = 4Mpixels/second (Mode 3)

Maximum pixel rate = 6Mpixels/second (Mode 4)

SYSTEM

ASIC

Figure 24 Block Diagram of Monochrome CCD Application, AC Coupled

SETTING

NAME

ADDRESS

HEX

BINARY

NOTE

Set-up

000001

0010 1111

EN = 1: Device enabled;

CDS = 1: CDS enabled;

MONO = 1: Monochrome operation;

SELPD = 1: Selective power down possible;

PGAFS[1:0] = 10: ADC range optimised for

negative going video;

MODE4 = 0: Only set when 2:1 MCLK:VSMP

ratio required (mode 4).

Set-up

000010

0010 0000

MUXOP[1:0] = 00: 12-bit parallel output;

INVOP = 0: Output data not inverted;

VRLCEXT = 0: RLCDAC required to provide

reset level clamp voltage since sensor is

AC coupled;

RLCDACRNG = 1: RLCDAC range is 0V to VRT;

DEL[1:0] = 00: Default latency.

Set-up

000011

0001 1111

RLCV[3:0] = 1111: RLCDAC full scale voltage;

CDSREF[1:0] = 01: Default reset sample

position;

CHAN[1:0] = 00: Red channel selected.

Set-up

000101

0000 0000

Line-by-line mode not used so this register is

not required.

Set-up

001000

0000 0000

Only used if programmable VSMP circuit is

required.

Set-up

001001

0000 0110

SELDIS[3:0] = 0110: Disable green and blue

channels to reduce power.

Table 8

Typical Control Register Settings for Figure 24 (CDS, Negative-Going CCD

Video Signal, MCLK:VSMP = 2:1/3:1/6:1/8:1)

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