WM8141

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 3.0 October 2000

16

CONTROL INTERFACE

The internal control registers are programmable via the serial or parallel digital control interface. The

register contents can also be read back via the parallel interface on OP[11:4], or via the serial

interface on pin OP[11]/SDO.

SERIAL INTERFACE: REGISTER WRITE

Figure 12 shows register writing in serial mode. Three pins, SCK, SDI and SEN are used. A six-bit

address (a5, 0, a3, a2, a1, a0) is clocked in through SDI, MSB first, followed by an eight-bit data

word (b7, b6, b5, b4, b3, b2, b1, b0), also MSB first. Each bit is latched on the rising edge of SCK.

When the data has been shifted into the device, a pulse is applied to SEN to transfer the data to the

appropriate internal register. Note all valid registers have address bit a4 equal to 0 in write mode.

SCK

SEN

SDI

a5

0

a3a2a1a0b7b6b5b4b3b2b1b0

Address

Data Word

Figure 12 Serial Interface Register Write

SERIAL INTERFACE: REGISTER READ-BACK

Figure 13 shows register read-back in serial mode. Read-back is initiated by writing to the serial bus

as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. Writing

address (a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of

corresponding register (a5, 0, a3, a2, a1, a0) to be output MSB first on pin SDO (on the falling edge

of SCK). Note that pin SDO is shared with an output pin, OP[11], therefore OEB should always be

held low when register read-back data is expected on this pin. The next word may be read in to SDI

while the previous word is still being output on SDO.

SCK

SEN

SDI

a5

1

a3 a2 a1 a0

xxxxx

xx

x

Address

Data Word

d7 d6 d5 d4 d3 d2 d1 d0

Output Data Word

SDO/

OP[11]

OEB

Figure 13 Serial Interface Register Read-back

PARALLEL INTERFACE: REGISTER WRITE

Figure 13 shows register write in parallel mode. The parallel interface uses bits OP[11:4] of the

output bus and the STB, DNA and RNW pins. Pin RNW must be low during a write operation. The

DNA pin defines whether the data byte is address (low) or data (high). The 6-bit address (a5, 0, a3,

a2, a1, a0) is input into OP[9:4], LSB into OP[4], (OP[10] and OP[11] are ignored) when DNA is low,

then the 8-bit data word is input into OP[11:4], LSB into OP[4], when DNA is high. The data bus

OP[11:4] for both address and data is clocked in on the falling edge of STB. Note all valid registers

have address bit a4 equal to 0.