Production Data

WM8141

WOLFSON MICROELECTRONICS LTD

PD Rev 3.0 October 2000

19

LINE-BY-LINE OPERATION

Certain linear sensors (e.g Contact Image Sensors) give colour output on a line-by-line basis. i.e a

full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to

accommodate this type of signal the WM8141 can be set into Monochrome mode, with the input

channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8141

can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is

set the green and blue processing channels are powered down and the device is forced internally to

only operate in MONO mode (because only one colour is sampled at a time) through the red channel.

Figure 17 shows the signal path when operating in colour line-by-line mode.

RINP

SEN/STB

VSMP

MCLK

VRLC/VBIAS

SDI/DNA

SCK/RNW

RLC/ACYC

RLC

BINP

GINP

INPUT

MUX

OFFSET

MUX

RLC

RLC

R

G

B

R

G

B

PGA

I/P SIGNAL

POLARITY

ADJUST

8

RLC

DAC

+

CONFIGURABLE

SERIAL/

PARALLEL

CONTROL

INTERFACE

OP[11:0]

+

WM8141

12-BIT

ADC

DATA

I/O

PORT

8

OFFSET

DAC

PGA

MUX

TIMING CONTROL

CL

V

S

R

S

4

CDS

Figure 17 Signal Path When in Line-by-Line Mode

In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be auto-

cycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit.

The multiplexers change on the first MCLK rising edge after RLC/ACYC is taken high. Alternatively,

all three multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to

select the desired colour. It is also possible for the input multiplexer to be controlled separately from

the PGA and Offset multiplexers. Table 4 describes all the multiplexer selection modes that are

possible.

FME

ACYCNRLC

NAME

DESCRIPTION

00

Internal,

no force mux

Input mux, offset and gain registers determined by

internal register bits INTM1, INTM0.

01

Auto-cycling,

no force mux

Input mux, offset and gain registers auto-cycled, RINP

→ GINP → BINP → RINP… on RLC/ACYC pulse.

10

Internal,

force mux

Input mux selected from internal register bits FM1, FM0;

Offset and gain registers selected from internal register

bits INTM1, INTM0.

11

Auto-cycling,

force mux

Input mux selected from internal register bits FM1, FM0;

Offset and gain registers auto-cycled, RINP

→ GINP →

BINP

→ RINP… on RLC/ACYC pulse.

Table 4 Colour Selection Description in Line-by-Line Mode