WM2633

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 1999

10

SOFTWARE CONFIGURATION OPTIONS

DATA FORMAT

The WM2613 writes data either to one of the DAC holding latches or to the control register

depending on the address bits A1 and A0.

A1

A0

LATCH

D7D6D5

D4D3D2

D1D0

00

DAC LSW holding

DAC 7

DAC 6

DAC 5

DAC 4

DAC 3

DAC2

DAC 1

DAC 0

01

DAC MSW holding

X

X

X

X

DAC 11 DAC 10

DAC 9

DAC 8

10

Reserved

000

000

00

11

Control

X

X

X

REF1

REF0

RLDAC

PWR

SPD

Table 2 Register Map

PROGRAMMABLE SETTLING TIME

Settling time is a software selectable 3.5

µs or 1µs, typical to within ±0.5LSB of final value. This is

controlled by the value of SPD – Bit D12. A ONE defines a settling time of 1

µs, a ZERO defines a

settling time of 3.5

µs.

PIN

BIT

SPD

SPD

MODE

00

Slow

01

Fast

10

Fast

11

Fast

Table 3 Programmable Settling Time

PROGRAMMABLE POWER DOWN

The power down function can be controlled by PWR. A ZERO configures the device as active, or fully

powered up, a ONE configures the device into power down mode. When the power down function is

released the device reverts to the DAC code set prior to power down.

PIN

BIT

NPD

PWD

POWER

00

Down

01

Down

10

Normal

11

Down

Table 4 Programmable Power Down

LOAD DAC LATCH

Bit RLDAC controls the function of the DAC latch. A ONE configures the DAC latch as transparent. A

ZERO configures the DAC latch to be controlled by pin NLDAC.

PIN

BIT

NLDAC

RLDAC

LATCH

0

0

Transparent

0

1

Transparent

10

Hold

1

1

Transparent

Table 5 Load DAC Latch