Production Data

WM2633

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 July 1999

9

PARALLEL INTERFACE

The device latches data on the positive edge of NWE. It must be enabled with NCS low. Whether the

data is written to one of the DAC holding latches (MSW, LSW) or the control register, depends on the

address bits A1 and A0. NLDAC low updates the DAC with the value in the holding latch. NLDAC is

an asynchronous input and can be held low, if a synchronous update is not necessary. Alternatively,

the RLDAC bit of the control register can be used to synchonously update the DAC latch via software

control.

D[0-7]

A[0-1]

NCS

NWE

NLDAC

X

MSW

LSW

XX

10

XX

Figure 7 Example of a Complete Write Cycle Using NLDAC to Update the DAC

D[0-7]

A[0-1]

NCS

NWE

NLDAC

X

MSW

LSW

X

01

X

Control

X

X

X

3

X

X

Figure 8 Example of a Complete Write Cycle Using the Control Word to Update the DAC. If NLDAC is held high as

shown above, the DAC latch is normally closed, but can be made transparent by setting the RLDAC control register bit

high. The procedure shown assumes that the RLDAC bit is low at the start and is written high on the final write.