TS8GDOM40V datasheet(34/52 Pages) TRANSCEND

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Transcend Information Inc.

Ver 1.7

Ultra DMA Data Burst Timing Descriptions

Name

Comment

Notes

t2CYCTYP

Typical sustained average two cycle time

tCYC

Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE

edge)

t2CYC

Two cycle time allowing for clock variations (from rising edge to next rising edge or from

falling edge to next falling edge of STROBE)

tDS

Data setup time at recipient (from data valid until STROBE edge)

tDH

Data hold time at recipient (from STROBE edge until data may become invalid)

tDVS

Data valid setup time at sender (from data valid until STROBE edge)

tDVH

Data valid hold time at sender (from STROBE edge until data may become invalid)

tCS

CRC word setup time at device

tCH

CRC word hold time device

tCVS

CRC word valid setup time at host (from CRC valid until -DMACK negation)

tCVH

CRC word valid hold time at sender (from -DMACK negation until CRC may become invalid) 3

tZFS

Time from STROBE output released-to-driving until the first transition of critical timing.

tDZFS

Time from data output released-to-driving until the first transition of critical timing.

tFS

First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)

tLI

Limited interlock time

tMLI

Interlock time with minimum

tUI

Unlimited interlock time

tAZ

Maximum time allowed for output drivers to release (from asserted or negated)

tZAH

Minimum delay time required for output

tZAD

drivers to assert or negate (from released)

tENV

Envelope time (from -DMACK to STOP and -HDMARDY during data in burst initiation and

from DMACK to STOP during data out burst initiation)

tRFS

Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of

-DMARDY)

tRP

Ready-to-pause time (that recipient shall wait to pause after negating -DMARDY)

tIORDYZ

Maximum time before releasing IORDY

tZIORDY

Minimum time before driving IORDY

tACK

Setup and hold times for -DMACK (before assertion or negation)

tSS

Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender

terminates a burst)

Notes:

(1) The parameters tUI, tMLI (in Page 19: Ultra DMA Data-In Burst Device Termination Timing and Page 20: Ultra DMA Data-In

Burst Host Termination Timing), and tLI indicate sender-to-recipient or recipient-to-sender interlocks,i.e., one agent

(either sender or recipient) is waiting for the other agent to respond with a signal before proceeding.tUI is an unlimited

interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a limited time-out

that has a defined maximum.

(2) 80-conductor cabling (see see ATA specification :Annex A)) shall be required in order to meet setup (tDS, tCS) and hold (tDH,

tCH) times in modes greater than 2.

(3) Timing for

tDVS, tDVH, tCVS and tCVH shall be met for lumped capacitive loads of 15 and 40 pF at the connector where

the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing

measurements are not valid in a normally functioning system.

(4) For all timing modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a pull-up on IORDY-

giving it a known state when released.

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