TS8GDOM40V datasheet(29/52 Pages) TRANSCEND

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Transcend Information Inc.

Ver 1.7

True IDE Multiword DMA Mode Read/Write Timing Specification

Item

Mode 0

(ns)

Mode 1

(ns)

Mode 2

(ns)

Mode 3

(ns)

Mode 4

(ns)

Cycle time (min)

480

150

120

100

-IORD / -IOWR asserted width(min)

215

-IORD data access (max)

150

-IORD data hold (min)

tG -IORD/-IOWR data setup (min)

100

tH -IOWR data hold (min)

DMACK to –IORD/-IOWR setup (min)

-IORD / -IOWR to -DMACK hold (min)

tKR -IORD negated width (min) 1

tKW -IOWR negated width (min) 1

215

tLR -IORD to DMARQ delay (max)

120

tLW -IOWR to DMARQ delay (max)

tM CS(1:0) valid to –IORD / -IOWR

CS(1:0) hold

-DMACK

Notes:

(1) t0 is the minimum total cycle time and tD is the minimum command active time, while tKR and tKW are the

minimum command recovery time or command inactive time for input and output cycles respectively. The

actual cycle time equals the sum of the actual command active time and the actual command inactive time.

The three timing requirements of t0, tD, tKR, and tKW shall be met. The minimum total cycle time requirement

is greater than the sum of tD and tKR or tKW.for input and output cycles respectively. This means a host

implementation can lengthen either or both of tD and either of tKR, and tKW as needed to ensure that t0 is

equal to or greater than the value reported in the device’s identify device data.

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