AD9575

Rev. 0 | Page 13 of 16

3.3V

LVPECL

DIFFERENTIAL

(COUPLED)

3.3V

LVPECL

100Ω

0.1nF

0.1nF

200Ω

200Ω

Figure 19. LVPECL with Parallel Transmission Line

LVDS CLOCK DISTRIBUTION

The AD9575 is also available with low voltage differential

signaling (LVDS) outputs. LVDS uses a current mode output

stage with a factory programmed current level. The normal

value (default) for this current is 3.5 mA, which yields a 350 mV

output swing across a 100 Ω resistor. The LVDS outputs meet or

exceed all ANSI/TIA/EIA-644 specifications.

A recommended termination circuit for the LVDS outputs is

shown in Figure 20.

50Ω

50Ω

LVDS

LVDS

100Ω

Figure 20. LVDS Output Termination

See the AN-586 Application Note on the Analog Devices

website at www.analog.com for more information about LVDS.

LVCMOS CLOCK DISTRIBUTION

The AD9575 provides a 33.33 or 62.5 MHz clock output, which

is a dedicated LVCMOS level. Whenever single-ended LVCMOS

clocking is used, some of the following general guidelines

should be followed.

Point-to-point nets should be designed such that a driver has

one receiver only on the net, if possible. This allows for simple

termination schemes and minimizes ringing due to possible

mismatched impedances on the net. Series termination at the

source is generally required to provide transmission line

matching and/or to reduce current transients at the driver (see

Figure 21). The value of the resistor is dependent on the board

design and timing requirements (typically 10 Ω to 100 Ω is

used). LVCMOS outputs are limited in terms of the capacitive

load or trace length that they can drive. Typically, trace lengths

less than 6 inches are recommended to preserve signal rise/fall

times and preserve signal integrity.

10Ω

MICROSTRIP

GND

5pF

60.4Ω

1.0 INCH

CMOS

Figure 21. Series Termination of LVCMOS Output

Termination at the far end of the PCB trace is a second option.

The LVCMOS output of the AD9575 does not supply enough

current to provide a full voltage swing with a low impedance

resistive, far-end termination, as shown in Figure 22. The far-end

termination network should match the PCB trace impedance

and provide the desired switching point.

The reduced signal swing may still meet receiver input

requirements in some applications. This can be useful when

driving long trace lengths on less critical nets.

50Ω

10Ω

LVCMOS

3pF

100Ω

100Ω

Figure 22. LVCMOS Output with Far-End Termination

TYPICAL APPLICATIONS

1

2

3

4

5

6

7

8

VDDA

VDDX

XO1

GNDA

GNDX

XO2

GNDA

VDDA

16

15

14

13

12

11

10

9

GND

LVDS/LVPECL OUT

LVDS/LVPECL OUT

CMOS OUT/SEL1

GND CMOS

VDD_CMOS

VDD

SEL0

AD9575

50Ω

100Ω

50Ω

1nF

0.1µF

0.1µF

0.1µF

0.1µF

0.1µF

Cx

Cx

Figure 23. Typical Application (in LVDS configuration)