Network Clock Generator, Two Outputs

AD9575

Rev. 0

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responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

©2010 Analog Devices, Inc. All rights reserved.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother

rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

©2010 Analog Devices, Inc. All rights reserved.

FEATURES

Fully integrated VCO/PLL core

0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz

0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz

0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz

0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz

Input crystal frequency of 19.44 MHz, 25 MHz, or

25.78125 MHz

Pin selectable divide ratios for 33.33 MHz, 62.5 MHz,

100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz,

159.375 MHz, 161.13 MHz, and 312.5 MHz outputs

LVDS/LVPECL/LVCMOS output format

Integrated loop filter

Space saving 4.4 mm × 5.0 mm TSSOP

100 mW power dissipation (LVDS output)

120 mW power dissipation (LVPECL output)

3.3 V operation

APPLICATIONS

GbE/FC/SONET line cards, switches, and routers

CPU/PCI-e applications

Low jitter, low phase noise clock generation

GENERAL DESCRIPTION

The AD9575 provides a highly integrated, dual output clock

generator function including an on-chip PLL core that is

optimized for network clocking. The integer-N PLL design is

based on the Analog Devices, Inc., proven portfolio of high

performance, low jitter frequency synthesizers to maximize line

card performance. Other applications with demanding phase

noise and jitter requirements also benefit from this part.

The PLL section consists of a low noise phase frequency detector

(PFD), a precision charge pump, a low phase noise voltage

controlled oscillator (VCO), and pin selectable feedback and

output dividers.

By connecting an external crystal, popular network output

frequencies can be locked to the input reference. The output

divider and feedback divider ratios are pin programmable for the

required output rates. No external loop filter components are

required, thus conserving valuable design time and board space.

The AD9575 is available in a 16-lead, 4.4 mm × 5.0 mm TSSOP

and can be operated from a single 3.3 V supply. The temperature

range is −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

VDD × 5

GND × 5

AD9575

XTAL

OSC

VCO

100MHz

TO 312.5MHz

LVDS OR

LVPECL

LVCMOS

33.33MHz/

62.5MHz/SEL1

LDO

SEL0

SEL

Figure 1.