AD9575

Rev. 0 | Page 12 of 16

THEORY OF OPERATION

XTAL

OSC

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

1/n

1/k

SEL

LVCMOS

CMOS OUT/SEL1

VDDA GNDA

VDDA GNDA

VDD_CMOS

GND_CMOS

SEL0

1/m

2.5GHz TO

2.55GHz VCO

LVDS

100MHz

AD9575

LDO

LVDS/LVPECL OUT

LVDS/LVPECL OUT

Figure 16. Detailed Block Diagram

Figure 16 shows a block diagram of the AD9575. The chip

features a PLL core, which is configured to generate the specific

clock frequencies via pin programming. By appropriate connec-

tion of the select pins, SEL0 and SEL1, as described in Table 12,

the divide ratios of the feedback divider (n), LVDS output

divider (m), and LVCMOS output divider (k) can be programmed.

In Mode 1 and Mode 4, Pin 10 is configured as a LVCMOS

output by forcing Pin 16 to GND. In conjunction with a band-

select VCO that operates over the range of 2.488 GHz to 2.55 GHz,

a wide range of popular network reference frequencies can

be generated. This PLL is based on proven Analog Devices

synthesizer technology, noted for its exceptional phase noise

performance. The AD9575 is highly integrated and includes

the loop filter, a regulator for supply noise immunity, all the

necessary dividers, output buffers, and a crystal oscillator. A

user need only supply an external crystal to implement a

clocking solution, which does not require any processor

intervention.

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the reference clock and feedback

divider to produce an output proportional to the phase and

frequency difference between them. Figure 17 shows a

simplified schematic.

D1 Q1

CLR1

REFCLK

HIGH

UP

D2 Q2

CLR2

HIGH

DOWN

CP

CHARGE

PUMP

GND

FEEDBACK

DIVIDER

Figure 17. PFD Simplified Schematic and Timing (in Lock)

POWER SUPPLY

Specifications section gives the performance expected from the

AD9575 with the power supply voltage within this range. The

absolute maximum range of −0.3 V to +3.6 V, with respect to

GND, must never be exceeded on the VDDX, VDD_CMOS,

and VDDA pins.

Good engineering practice should be followed in the layout of

power supply traces and the ground plane of the PCB. The

power supply should be bypassed on the PCB with adequate

capacitance (>10 μF). The AD9575 should be bypassed with

adequate capacitors (0.1 μF) at all power pins as close as

possible to the part. The layout of the AD9575 evaluation board

is a good example.

LVPECL CLOCK DISTRIBUTION

The LVPECL outputs (because they are open emitter) require a

dc termination to bias the output transistors. The simplified

equivalent circuit in Figure 19 shows the LVPECL output stage.

In most applications, a standard LVPECL far-end termination is

recommended, as shown in Figure 18. The resistor network is

designed to match the transmission line impedance (50 Ω) and

the desired switching threshold (1.3 V).

3.3V

50Ω

50Ω

SINGLE-ENDED

(NOT COUPLED)

3.3V

3.3V

LVPECL

127Ω

127Ω

83Ω

83Ω

LVPECL

Figure 18. LVPECL Far-End Termination