LPC2364 datasheet(2/59 Pages) NXP

2 / 59 page

LPC2364_65_66_67_68_6

Product data sheet

Rev. 06 — 1 February 2010

2 of 59

NXP Semiconductors

LPC2364/65/66/67/68

Single-chip 16-bit/32-bit microcontrollers

Serial interfaces:

Ethernet MAC with associated DMA controller. These functions reside on an

independent AHB.

USB 2.0 full-speed device with on-chip PHY and associated DMA controller

(LPC2364/66/68 only).

Four UARTs with fractional baud rate generation, one with modem control I/O, one

with IrDA support, all with FIFO.

CAN controller with two channels (LPC2364/66/68 only).

SPI controller.

Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate

for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA

controller.

Three I2C-bus interfaces (one with open-drain and two with standard port pins).

I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with

the GPDMA.

Other peripherals:

SD/MMC memory card interface (LPC2367/68 only).

70 general purpose I/O pins with configurable pull-up/down resistors.

10-bit ADC with input multiplexing among 6 pins.

10-bit DAC.

Four general purpose timers/counters with a total of 8 capture inputs and 10

compare outputs. Each timer block has an external count input.

One PWM/timer block with support for three-phase motor control. The PWM has

two external count inputs.

Real-Time Clock (RTC) with separate power pin, clock source can be the RTC

oscillator or the APB clock.

2 kB SRAM powered from the RTC power pin, allowing data to be stored when the

rest of the chip is powered off.

WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,

the RTC oscillator, or the APB clock.

Standard ARM test/debug interface for compatibility with existing tools.

Emulation trace module supports real-time trace.

Single 3.3 V power supply (3.0 V to 3.6 V).

Four reduced power modes: idle, sleep, power-down, and deep power-down.

Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0

and Port 2 can be used as edge sensitive interrupt sources.

Processor wake-up from Power-down mode via any interrupt able to operate during

Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet

wake-up interrupt).

Two independent power domains allow fine tuning of power consumption based on

needed features.

Each peripheral has its own clock divider for further power saving.

Brownout detect with separate thresholds for interrupt and forced reset.

On-chip power-on reset.

On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz.

4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as

the system clock. When used as the CPU clock, does not allow CAN and USB to run.

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