MPC8548E datasheet(18/144 Pages) FREESCALE

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MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6

Freescale Semiconductor

RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of

the MPC8548E. Table 8 provides the RESET initialization AC timing specifications for the DDR SDRAM

component(s).

Table 9 provides the PLL lock times.

5.1

Power-On Ramp Rate

This section describes the AC electrical specifications for the power-on ramp rate requirements.

Controlling the maximum power-on ramp rate is required to avoid falsely triggering the ESD circuitry.

Table 10 provides the power supply ramp rate specifications.

Table 8. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET

100

—

μs—

Minimum assertion time for SRESET

—

SYSCLKs

PLL input setup time with stable SYSCLK before HRESET negation

100

—

μs—

Input setup time for POR configs (other than PLL config) with respect to

negation of HRESET

—

SYSCLKs

Input hold time for all POR configs (including PLL config) with respect to

negation of HRESET

—

SYSCLKs

Maximum valid-to-high impedance time for actively driven POR configs with

respect to negation of HRESET

—

SYSCLKs

Note:

1. SYSCLK is the primary clock input for the MPC8548E.

Table 9. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Core and platform PLL lock times

—

100

μs

Local bus PLL lock time

—

μs

PCI/PCI-X bus PLL lock time

—

μs

Table 10. Power Supply Ramp Rate

Parameter

Min

Max

Unit

Notes

Required ramp rate for MVREF

—

3500

V/s

Required ramp rate for VDD

—

4000

V/s

1, 2

Note:

1. Maximum ramp rate from 200 to 500 mV is most critical as this range may falsely trigger the ESD circuitry.

2. VDD itself is not vulnerable to false ESD triggering; however, as per Section 21.2, “PLL Power Supply Filtering,” the

recommended AVDD_CORE, AVDD_PLAT, AVDD_LBIU, AVDD_PCI1 and AVDD_PCI2 filters are all connected to VDD.

Their ramp rates should be equal to or less than the VDD ramp rate.

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