MPC8548E datasheet(60/144 Pages) FREESCALE

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MPC8548E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 6

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

15 High-Speed Serial Interfaces (HSSI)

The MPC8548E features one Serializer/Deserializer (SerDes) interface to be used for high-speed serial

interconnect applications. The SerDes interface can be used for PCI Express and/or serial RapidIO data

transfers.

This section describes the common portion of SerDes DC electrical specifications, which is the DC

requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits

are also shown.

15.1

Signal Terms Definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms

used in the description and specification of differential signals.

Figure 38 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for the

description. The figure shows a waveform for either a transmitter output (SD_TX and SD_TX) or a

receiver input (SD_RX and SD_RX). Each signal swings between A volts and B volts where A > B.

HRESET to PCI-X initialization pattern hold time

tPCRHIX

050

6, 12

Notes:

1. See the timing measurement conditions in the

PCI-X 1.0a Specification.

2. Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and

load circuit.

3. Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused.

4. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

5. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time.

6. Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, tPCRHFV).

The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks

before the first FRAME and must be floated no later than one clock before FRAME is asserted.

7. A PCI-X device is permitted to have the minimum values shown for tPCKHOV and tCYC only in PCI-X mode. In conventional

mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency.

8. Device must meet this specification independent of how many outputs switch simultaneously.

9. The timing parameter tPCIVKH is a minimum of 1.4 ns rather than the minimum of 1.2 ns in the PCI-X 1.0a Specification.

10.The timing parameter tPCRHFV is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a

Specification.

11.Guaranteed by characterization.

11.Guaranteed by design.

Table 50. PCI-X AC Timing Specifications at 133 MHz (continued)

Parameter

Symbol

Min

Max

Unit

Notes

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