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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9393/PCBZ датащи(PDF) 15 Page - Analog Devices |
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AD9393/PCBZ датащи(HTML) 15 Page - Analog Devices |
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15 / 40 page  AD9393 Rev. 0 | Page 15 of 40 Hex Address Read/Write Bits Default Value Register Name Description 0x47 Read/write [4:0] xxx01000 CSC_COEFF_C2 MSB MSB of Register 0x48. 0x48 Read/write [7:0] 00000000 CSC_COEFF_C2 LSB CSC coefficient for equation: ROUT = (A1 × RIN) + (A2 × GIN) + (A3 × BIN) + A4 GOUT = (B1 × RIN) + (B2 × GIN) + (B3 × BIN) + B4 BOUT = (C1 × RIN) + (C2 × GIN) + (C3 × BIN) + C4 0x49 Read/write [4:0] xxx01110 CSC_COEFF_C3 MSB MSB of Register 0x4A. 0x4A Read/write [7:0] 10000111 CSC_COEFF_C3 LSB CSC coefficient for equation: ROUT = (A1 × RIN) + (A2 × GIN) + (A3 × BIN) + A4 GOUT = (B1 × RIN) + (B2 × GIN) + (B3 × BIN) + B4 BOUT = (C1 × RIN) + (C2 × GIN) + (C3 × BIN) + C4 0x4B Read/write [4:0] xxx11000 CSC_COEFF_C4 MSB MSB of Register 0x4C. 0x4C Read/write [7:0] 10111101 CSC_COEFF_C4 LSB CSC coefficient for equation: ROUT = (A1 × RIN) + (A2 × GIN) + (A3 × BIN) + A4 GOUT = (B1 × RIN) + (B2 × GIN) + (B3 × BIN) + B4 BOUT = (C1 × RIN) + (C2 × GIN) + (C3 × BIN) + C4 0x4D Read/write [7:0] 00110110 TMDS PLL Control1 Must be written to 0x3B. 0x4E Read/write [7:0] 00110110 TMDS PLL Control2 Must be written to 0x6D. 0x4F Read/write [7:0] 00110110 TMDS PLL Control3 Must be written to 0x54. 0x50 Read/write [7:0] 00100000 Test Must be written to 0x20 for proper operation. 0x56 Read/write [7:0] 00001111 Test Must be written to 0x0F (default) for proper operation. 0x57 Read/write [7] 0xxxxxxx AV mute override A1 overrides the AV mute value with Bit 6. [6] x0xxxxxx AV mute value Sets AV mute value if override is enabled. [3] xxxx0xxx Disable video mute Disables mute of video during AV mute. [2] xxxxx0xx Disable audio mute Disables mute of audio during AV mute. 0x58 Read/write [7] 0 MCLK PLL enable MCLK PLL enable—uses analog PLL. [6:4] 0 MCLK PLL_N MCLK PLL_N [2:0]—this controls the division of the MCLK out of the PLL: 0 = /1, 1 = /2, 2 = /3, 3 = /4 … [3] 0 N_CTS_DISABLE Prevents the N/CTS packet on the link from writing to the N and CTS registers. [2:0] 0 MCLK FS_N Controls the multiple of 128 fS used for MCLK out. 0 = 128 × fS, 1 = 256 × fS, 2 = 384 × fS, 7 = 1024 × fS. 0x59 Read/write [6] 0 MDA/MCL PU This disables the MDA/MCL pull-ups. [5] 0 CLK term O/R Clock termination power-down override: 0 = auto, 1 = manual. [4] 0 Manual CLK term Clock termination: 0 = normal, 1 = disconnected. [2] 0 FIFO reset UF This bit resets the audio FIFO if underflow is detected. [1] 0 FIFO reset OF This bit resets the audio FIFO if overflow is detected. [0] 0 MDA/MCL three-state This bit three-states the MDA/MCL lines. 0x5A Read [6:0] 0 Packet detected These seven bits are updated if any specific packet has been received since last reset or loss of clock detect. Normal is 0x00. Bit Data Packet Detected 0 AVI infoframe. 1 Audio infoframe. 2 SPD infoframe. 3 MPEG source infoframe. 4 ACP packets. 5 ISRC1 packets. 6 ISRC2 packets. 0x5B Read [3] 0 HDMI mode 0 = DVI, 1 = HDMI. |
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