AD9393SLASHPCBZ datasheet(6/40 Pages) AD

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AD9393

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AD9393

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

D14

D15

D16

D18

D20

D22

DCLK

HSOUT

O/E

SDA

D13

D12

D17

D19

D21

D23

VDD

GND

SCLK

LRCLK

DVDD

VSOUT

SCL

GND

MCLK

I2S3

I2S2

I2S1

I2S0

SPDIF

RTERM

DDC_

SDA

Rx2+

RxC–

RxC+

GND

Rx0–

Rx0+

GND

Rx1–

Rx1+

GND

Rx2–

D11

D10

GND

FILT

GND

PVDD

MDA

PVDD

MCL

DDC_

SCL

GND

123

456

789

Figure 2. Pin Configuration

Table 4. Complete Pin List

Pin No.

Mnemonic

Description

Value

Inputs

Power-Down Control. Power-Down Control/Three-State Control. The function

of this pin is programmable via Register 0x26[2:1].

3.3 V CMOS

Digital Video Data Inputs

K5, K4, K8, K7, J10, K10

Rx0+, Rx0−,

Rx1+, Rx1−,

Rx2+, Rx2−

Digital Input Channel x True/Complement. These six pins receive three pairs of

transition minimized differential signaling (TMDS ) pixel data (at 10× the pixel

rate) from a digital graphics transmitter.

TMDS

Digital Video Clock Inputs

K2, K1

RxC+, RxC−

Digital Data Clock True/Complement. This clock pair receives a TMDS clock at

1× pixel data rate.

TMDS

Outputs

B6, A6, B5, A5, B4,

A4, B3, A3, A2, A1,

B1, B2, C1, C2, D1,

D2, E1, E2, F1, F2,

G1, G2, H1, H2

D[23:0]

Data Outputs. In RGB,

D[23:16] = Red[7:0]

D[15:8] = Green[7:0]

D[7:0] = Blue[7:0]

See Table 6

VDD

DCLK

Data Output Clock. This is the main clock output signal used to strobe the

output data and HSOUT into external logic. Four possible output clocks can

be selected with Register 0x25[7:6]. These are related to the pixel clock (½×

pixel clock, 1× pixel clock, 2× frequency pixel clock, and a 90° phase shifted

pixel clock). They are produced by the internal PLL clock generator and are

synchronous with the pixel clock. The polarity of DCLK can also be inverted via

VDD

HSOUT

HSYNC Output Clock (Phase-Aligned with DCLK). Horizontal sync output. A

reconstructed and phase-aligned version of the HSYNC input. Both the

polarity and duration of this output can be programmed via serial bus

registers. By maintaining alignment with DCLK and data, data timing with

respect to horizontal sync can always be determined.

VDD

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