ATmega328P datasheet(158/448 Pages) ATMEL

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8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

17.11 Register Description

17.11.1

TCCR2A – Timer/Counter Control Register A

• Bits 7:6 – COM2A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0

bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected

to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin

must be set in order to enable the output driver.

When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the

WGM22:0 bit setting. Table 17-2 shows the COM2A1:0 bit functionality when the WGM22:0 bits

are set to a normal or CTC mode (non-PWM).

Table 17-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM

mode.

Note:

1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com-

pare Match is ignored, but the set or clear is done at BOTTOM. See ”Fast PWM Mode” on

page 150 for more details.

Bit

210

(0xB0)

COM2A1

COM2A0

COM2B1

COM2B0

–

WGM21

WGM20

TCCR2A

Read/Write

R/W

Initial Value

Table 17-2.

Compare Output Mode, non-PWM Mode

COM2A1

COM2A0

Description

Normal port operation, OC0A disconnected.

Toggle OC2A on Compare Match

Clear OC2A on Compare Match

Set OC2A on Compare Match

Table 17-3.

Compare Output Mode, Fast PWM Mode

(1)

COM2A1

COM2A0

Description

Normal port operation, OC2A disconnected.

WGM22 = 0: Normal Port Operation, OC0A Disconnected.

WGM22 = 1: Toggle OC2A on Compare Match.

Clear OC2A on Compare Match, set OC2A at BOTTOM,

(non-inverting mode).

Set OC2A on Compare Match, clear OC2A at BOTTOM,

(inverting mode).

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