ATmega328P datasheet(156/448 Pages) ATMEL

156 / 448 page

156

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is

clocked asynchronously: When the interrupt condition is met, the wake up process is started

on the following cycle of the timer clock, that is, the timer is always advanced by at least one

before the processor can read the counter value. After wake-up, the MCU is halted for four

cycles, it executes the interrupt routine, and resumes execution from the instruction following

SLEEP.

• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect

result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be

done through a register synchronized to the internal I/O clock domain. Synchronization takes

place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock

(clk

I/O) again becomes active, TCNT2 will read as the previous value (before entering sleep)

until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-

save mode is essentially unpredictable, as it depends on the wake-up time. The recommended

procedure for reading TCNT2 is thus as follows:

Write any value to either of the registers OCR2x or TCCR2x.

Wait for the corresponding Update Busy Flag to be cleared.

Read TCNT2.

During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous

timer takes 3 processor cycles plus one timer cycle. The timer is therefore advanced by at least

one before the processor can read the timer value causing the setting of the Interrupt Flag. The

Output Compare pin is changed on the timer clock and is not synchronized to the processor

clock.

17.10 Timer/Counter Prescaler

Figure 17-12. Prescaler for Timer/Counter2

The clock source for Timer/Counter2 is named clk

T2S. clkT2S is by default connected to the main

system I/O clock clk

IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously

clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter

10-BIT T/C PRESCALER

TIMER/COUNTER2 CLOCK SOURCE

clk

I/O

clk

T2S

TOSC1

AS2

CS20

CS21

CS22

PSRASY

Clear

clk

ATmega328P датащи(PDF) 156 Page - ATMEL Corporation

ATmega328P датащи(HTML) 156 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL