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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega328P датащи(PDF) 139 Page - ATMEL Corporation |
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ATmega328P датащи(HTML) 139 Page - ATMEL Corporation |
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139 / 448 page  139 8161D–AVR–10/09 ATmega48PA/88PA/168PA/328P The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See Section “15.3” on page 115. 15.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the ATmega48PA/88PA/168PA/328P, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 57) is executed when the ICF1 Flag, located in TIFR1, is set. • Bit 4, 3 – Res: Reserved Bits These bits are unused bits in the ATmega48PA/88PA/168PA/328P, and will always read as zero. • Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 57) is executed when the OCF1B Flag, located in TIFR1, is set. • Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 57) is executed when the OCF1A Flag, located in TIFR1, is set. • Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See ”Interrupts” on page 57) is executed when the TOV1 Flag, located in TIFR1, is set. 15.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the ATmega48PA/88PA/168PA/328P, and will always read as zero. Bit 7654 3 2 1 0 (0x6F) – – ICIE1 – – OCIE1B OCIE1A TOIE1 TIMSK1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0000 0 0 0 0 Bit 7 654 32 10 0x16 (0x36) – – ICF1 – – OCF1B OCF1A TOV1 TIFR1 Read/Write R R R/W R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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