ATmega328P datasheet(134/448 Pages) ATMEL

134 / 448 page

134

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

Figure 15-13 shows the same timing data, but with the prescaler enabled.

Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O/8)

15.11 Register Description

15.11.1

TCCR1A – Timer/Counter1 Control Register A

• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A

• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B

The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respec-

tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output

overrides the normal port functionality of the I/O pin it is connected to. If one or both of the

COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the

I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-

ing to the OC1A or OC1B pin must be set in order to enable the output driver.

When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen-

dent of the WGM13:0 bits setting. Table 15-1 shows the COM1x1:0 bit functionality when the

WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).

TOVn(FPWM)

and ICF n(if used

as TOP)

OCRnx

(Update at TOP)

TCNTn

(CTC and FPWM)

TCNTn

(PC and PFC PWM)

TOP - 1

TOP

TOP - 1

TOP - 2

Old OCRnx Value

New OCRnx Value

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

Bit

7654

(0x80)

COM1A1

COM1A0

COM1B1

COM1B0

–

WGM11

WGM10

TCCR1A

Read/Write

R/W

Initial Value

0000

Table 15-1.

Compare Output Mode, non-PWM

COM1A1/COM1B1

COM1A0/COM1B0

Description

Normal port operation, OC1A/OC1B disconnected.

Toggle OC1A/OC1B on Compare Match.

Clear OC1A/OC1B on Compare Match (Set output to

low level).

Set OC1A/OC1B on Compare Match (Set output to

high level).

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