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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega328P датащи(PDF) 112 Page - ATMEL Corporation |
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ATmega328P датащи(HTML) 112 Page - ATMEL Corporation |
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112 / 448 page  112 8161D–AVR–10/09 ATmega48PA/88PA/168PA/328P the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 14-8, ”Waveform Generation Mode Bit Description” on page 108. |
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