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ATmega1284P датащи(PDF) 82 Page - ATMEL Corporation |
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ATmega1284P датащи(HTML) 82 Page - ATMEL Corporation |
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82 / 380 page ![]() 82 8059D–AVR–11/09 ATmega1284P CLKO, Divided System Clock: The divided system clock can be output on the PB1 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB1 and DDB1 settings. It will also be output during reset. PCINT9, Pin Change Interrupt source 9: The PB1 pin can serve as an external interrupt source. • T0/XCK0/PCINT8, Bit 0 T0, Timer/Counter0 counter source. XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode. PCINT8, Pin Change Interrupt source 8: The PB0 pin can serve as an external interrupt source. Table 12-7 and Table 12-8 relate the alternate functions of Port B to the overriding signals shown in Figure 12-5 on page 76. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. . Table 12-7. Overriding Signals for Alternate Functions in PB7:PB4 Signal Name PB7/SCK/ OC3B/PCINT15 PB6/MISO/ OC3A/PCINT14 PB5/MOSI/ ICP3/PCINT13 PB4/SS/OC0B/ PCINT12 PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR PUOV PORTB7 • PUD PORTB14 • PUD PORTB13 • PUD PORTB12 • PUD DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR DDOV 0 0 0 0 PVOE SPE • MSTR OC3B ENABLE SPE • MSTR OC3A ENABLE SPE • MSTR OC0A ENABLE PVOV SCK OUTPUT OC3B SPI SLAVE OUTPUT OC3A SPI MSTR OUTPUT OC0A DIEOE PCINT15 • PCIE1 PCINT14 • PCIE1 PCINT13 • PCIE1 PCINT4 • PCIE1 DIEOV 1 1 1 1 DI SCK INPUT PCINT17 INPUT SPI MSTR INPUT PCINT14 INPUT SPI SLAVE INPUT PCINT13 INPUT ICP3 INPUT SPI SS PCINT12 INPUT AIO – – – – |
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