ATmega1284P datasheet(66/380 Pages) ATMEL

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8059D–AVR–11/09

ATmega1284P

pletion of the currently executing instruction to generate an interrupt. If enabled, a level triggered

interrupt will generate an interrupt request as long as the pin is held low. When changing the

ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its

Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn

interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the

EIFR Register before the interrupt is re-enabled.

Note:

1. n = 3, 2, 1or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt

Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

11.2.2

EIMSK – External Interrupt Mask Register

• Bits 2:0 – INT2:0: External Interrupt Request 2 - 0 Enable

When an INT2:0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the

corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External

Interrupt Control Register, EICRA, defines whether the external interrupt is activated on rising or

falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if

the pin is enabled as an output. This provides a way of generating a software interrupt.

11.2.3

EIFR –External Interrupt Flag Register

• Bits 2:0 – INTF2:0: External Interrupt Flags 2 - 0

When an edge or logic change on the INT2:0 pin triggers an interrupt request, INTF2:0 becomes

set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT2:0 in EIMSK, are

set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine

is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are

always cleared when INT2:0 are configured as level interrupt. Note that when entering sleep

mode with the INT2:0 interrupts disabled, the input buffers on these pins will be disabled. This

may cause a logic change in internal signals which will set the INTF2:0 flags. See ”Digital Input

Enable and Sleep Modes” on page 74 for more information.

Table 11-1.

Interrupt Sense Control(1)

ISCn1

ISCn0

Description

The low level of INTn generates an interrupt request.

Any edge of INTn generates asynchronously an interrupt request.

The falling edge of INTn generates asynchronously an interrupt request.

The rising edge of INTn generates asynchronously an interrupt request.

Bit

76543210

0x1D (0x3D)

–

INT2

INT1

IINT0

EIMSK

Read/Write

RRRRR

R/W

Initial Value

00000000

Bit

76543210

0x1C (0x3C)

–

INTF2

INTF1

IINTF0

EIFR

Read/Write

R/W

RRRR

R/W

Initial Value

00000000

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