ATmega32HVB datasheet(199/273 Pages) ATMEL

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199

8042A–AVR–07/09

ATmega16HVB/32HVB

29.8.8

Reading the Fuse and Lock Bits from Software

It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the

Z-pointer with 0x0001 and set the LBSET and SPMEN bits in SPMCSR. When an LPM instruc-

tion is executed within three CPU cycles after the LBSET and SPMEN bits are set in SPMCSR,

the value of the Lock bits will be loaded in the destination register. The LBSET and SPMEN bits

will auto-clear upon completion of reading the Lock bits. When LBSET and SPMEN are cleared,

LPM will work as described in the ”AVR Instruction Set” description.

The algorithm for reading the Fuse Low byte is similar to the one described above for reading

the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the LBSET and

SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the

LBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be

loaded in the destination register as shown below. Refer to Table 30-4 on page 210 for a

detailed description and mapping of the Fuse Low byte.

Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc-

tion is executed within three cycles after the LBSET and SPMEN bits are set in the SPMCSR,

the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.

Refer to Table 30-3 on page 209 for detailed description and mapping of the Fuse High byte.

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are

unprogrammed, will be read as one.

29.8.9

Reading the Signature Row from Software

To read the Signature Row from software, load the Z-pointer with the signature byte address

given in Table 29-3 and set the SIGRD and SPMEN bits in SPMCSR. When an LPM instruction

is executed within three CPU cycles after the SIGRD and SPMEN bits are set in SPMCSR, the

signature byte value will be loaded in the destination register. The SIGRD and SPMEN bits will

auto-clear 6 cycles after writing to SPMCSR, which is locked for further writing during these

cycles. When SIGRD and SPMEN are cleared, LPM will work as described in the Instruction set

Manual

Bit

76543210

–

BLB12

BLB11

BLB02

BLB01

LB2

LB1

Bit

765

321

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Bit

321

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Table 29-3.

Signature Row Addressing.

Signature Byte Description

Z-Pointer Address

Device ID 0, Manufacture ID

00H

Device ID 1, Flash Size

02H

Device ID 2, Device

04H

FOSCCAL(1)

01H

FOSC SEGMENT(2)

03H

Reserved

05H

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