ATmega32HVB datasheet(17/273 Pages) ATMEL

17 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

AVR Memories

8.1

Overview

This section describes the different memories in the ATmega16HVB/32HVB. The AVR architec-

ture has two main memory spaces, the Data Memory and the Program Memory space. In

addition, the ATmega16HVB/32HVB features an EEPROM Memory for data storage. All three

memory spaces are linear and regular.

8.2

In-System Reprogrammable Flash Program Memory

The ATmega16HVB/32HVB contains 16K/32K bytes On-chip In-System Reprogrammable Flash

memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is orga-

nized as 8K/16K x 16.

The F lash memory has an endurance of at least 10,000 write/erase cycles. The

ATmega16HVB/32HVB Program Counter (PC) is 13/14 bits wide, thus addressing the 8K/16K

program memory locations. The operation of Boot Program section and associated Boot Lock

bits for software protection are described in detail in ”Boot Loader Support – Read-While-Write

Self-Programming” on page 191. ”Memory Programming” on page 208 contains a detailed

description on Flash programming.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-

ing” on page 14.

Figure 8-1.

Program Memory Map

8.3

SRAM Data Memory

Figure 8-2 on page 18 shows how the ATmega16HVB/32HVB SRAM Memory is organized.

0x0000

0x1FFF/0x3FFF

Program Memory

Application Flash Section

Boot Flash Section

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