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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega32HVB датащи(PDF) 60 Page - ATMEL Corporation |
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ATmega32HVB датащи(HTML) 60 Page - ATMEL Corporation |
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60 / 273 page  60 8042A–AVR–07/09 ATmega16HVB/32HVB 13.2.4 PCICR – Pin Change Interrupt Control Register • Bits 7:2 – RES: Reserved Bits These bits are reserved bits ins the ATmega16HVB/32HVB, and will always read as zero. • Bit 1 – PCIE1: Pin Change Interrupt Enable 1 When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT11..4 pin will cause an inter- rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT11..4 pins are enabled individually by the PCMSK1 Register. • Bit 0 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT3..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT3..0 pins are enabled individually by the PCMSK0 Register. 13.2.5 PCIFR – Pin Change Interrupt Flag Register • Bits 7:2 – RES: Reserved Bits These bits are reserved bits ins the ATmega16HVB/32HVB, and will always read as zero. • Bit 1 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT11..4 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. • Bit 0 – PCIF0: Pin Change Interrupt Flag 0 When a logic change on any PCINT3:0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. 13.2.6 PCMSK1 – Pin Change Mask Register 1 Bit 7 6543 210 (0x68) - ---- - PCIE1 PCIE0 PCICR Read/Write RRRR RR R/W R/W Initial Value 0 0000 000 Bit 7 6543 210 0x1B (0x3B) - ---- - PCIF1 PCIF0 PCIFR Read/Write RRRR RR R/W R/W Initial Value 0 0000 000 Bit 7 65 43 210 (0x6C) PCINT11 PCINT10 PCINT9 PCINT8 PCINT7 PCINT6 PCINT5 PCINT4 PCMSK1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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