ATmega325P datasheet(213/364 Pages) ATMEL

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213

8023F–AVR–07/09

ATmega325P/3250P

21.7.1

Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 21-8. An analog

source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard-

less of whether that channel is selected as input for the ADC. When the channel is selected, the

source must drive the S/H capacitor through the series resistance (combined resistance in the

input path).

The ADC is optimized for analog signals with an output impedance of approximately 10 k

Ω or

less. If such a source is used, the sampling time will be negligible. If a source with higher imped-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources

with slowly varying signals, since this minimizes the required charge transfer to the S/H

capacitor.

Signal components higher than the Nyquist frequency (f

ADC/2) should not be present for either

kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised

to remove high frequency components with a low-pass filter before applying the signals as

inputs to the ADC.

Figure 21-8. Analog Input Circuitry

21.7.2

Analog Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

analog measurements. If conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

Keep analog signal paths as short as possible. Make sure analog tracks run over the

analog ground plane, and keep them well away from high-speed switching digital tracks.

The AVCC pin on the device should be connected to the digital V

CC supply voltage via an

LC network as shown in Figure 21-9.

Use the ADC noise canceler function to reduce induced noise from the CPU.

If any ADC port pins are used as digital outputs, it is essential that these do not switch

while a conversion is in progress.

ADCn

IIH

1..100 k

CS/H= 14 pF

VCC/2

IIL

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