ATmega325P datasheet(92/364 Pages) ATMEL

92 / 364 page

8023F–AVR–07/09

ATmega325P/3250P

14.5

Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Register

(OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set

the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1 and

Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare

interrupt. The OCF0A Flag is automatically cleared when the interrupt is executed. Alternatively,

the OCF0A Flag can be cleared by software by writing a logical one to its I/O bit location. The

Waveform Generator uses the match signal to generate an output according to operating mode

set by the WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom sig-

nals are used by the Waveform Generator for handling the special cases of the extreme values

in some modes of operation (See Section “14.7” on page 94.).

Figure 14-3 shows a block diagram of the Output Compare unit.

Figure 14-3. Output Compare Unit, Block Diagram

The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-

ering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register

to either top or bottom of the counting sequence. The synchronization prevents the occurrence

of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0A Register access may seem complex, but this is not case. When the double buffer-

ing is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is

disabled the CPU will access the OCR0A directly.

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

OCnx

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnX1:0

bottom

ATmega325P датащи(PDF) 92 Page - ATMEL Corporation