ATmega325P datasheet(89/364 Pages) ATMEL

89 / 364 page

8023F–AVR–07/09

ATmega325P/3250P

14. 8-bit Timer/Counter0 with PWM

14.1

Features

• Single Compare Unit Counter

• Clear Timer on Compare Match (Auto Reload)

• Glitch-free, Phase Correct Pulse Width Modulator (PWM)

• Frequency Generator

• External Event Counter

• 10-bit Clock Prescaler

• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A)

14.2

Overview

Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simpli-

fied block diagram of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual placement

of I/O pins, refer to ”Pinout ATmega3250P” on page 2 and ”Pinout ATmega325P” on page 3.

CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-

specific I/O Register and bit locations are listed in the ”Register Description” on page 102.

Figure 14-1. 8-bit Timer/Counter Block Diagram

14.2.1

Registers

The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter-

rupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt

Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Reg-

ister (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk

T0).

Timer/Counter

TCNTn

Waveform

Generation

OCn

= 0

Control Logic

= 0xFF

BOTTOM

count

clear

direction

TOVn

(Int.Req.)

OCRn

TCCRn

Clock Select

Edge

Detector

( From Prescaler )

clkTn

TOP

OCn

(Int.Req.)

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