ATmega325P datasheet(138/364 Pages) ATMEL

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138

8023F–AVR–07/09

ATmega325P/3250P

Generator for handling the special cases of the extreme values in some modes of operation

(”Modes of Operation” on page 140).

Figure 16-3 shows a block diagram of the Output Compare unit.

Figure 16-3. Output Compare Unit, Block Diagram

The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM)

modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double

buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR2A Register access may seem complex, but this is not case. When the double buffer-

ing is enabled, the CPU has access to the OCR2A Buffer Register, and if double buffering is

disabled the CPU will access the OCR2A directly.

16.5.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC2A) bit. Forcing compare match will not set the

OCF2A Flag or reload/clear the timer, but the OC2A pin will be updated as if a real compare

match had occurred (the COM2A1:0 bits settings define whether the OC2A pin is set, cleared or

toggled).

16.5.2

Compare Match Blocking by TCNT2 Write

All CPU write operations to the TCNT2 Register will block any compare match that occurs in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR2A to be initial-

ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is

enabled.

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

OCnx

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnX1:0

bottom

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