ATmega325P datasheet(142/364 Pages) ATMEL

142 / 364 page

142

8023F–AVR–07/09

ATmega325P/3250P

16.7.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency

PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-

gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In

non-inverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare

match between TCNT2 and OCR2A, and set at BOTTOM. In inverting Compare Output mode,

the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation,

the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM

mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited

for power regulation, rectification, and DAC applications. High frequency allows physically small

sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the MAX value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 16-6. The TCNT2 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare

matches between OCR2A and TCNT2.

Figure 16-6. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin.

Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM2A1:0 to three (See Table 16-4 on page 150). The actual

OC2A value will only be visible on the port pin if the data direction for the port pin is set as out-

put. The PWM waveform is generated by setting (or clearing) the OC2A Register at the compare

match between OCR2A and TCNT2, and clearing (or setting) the OC2A Register at the timer

clock cycle the counter is cleared (changes from MAX to BOTTOM).

TCNTn

OCRnx Update and

TOVn Interrupt Flag Set

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Set

ATmega325P датащи(PDF) 142 Page - ATMEL Corporation