ATmega169P datasheet(310/393 Pages) ATMEL

310 / 393 page

310

8018N–AVR–08/09

ATmega169P

Figure 27-10. Serial Programming and Verify

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Notes:

1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High: > 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

27.8.2

Serial Programming Algorithm

When writing serial data to the ATmega169P, data is clocked on the rising edge of SCK.

When reading data from the ATmega169P, data is clocked on the falling edge of SCK. See Fig-

ure 27-11 for timing details.

To program and verify the ATmega169P in the serial programming mode, the following

sequence is recommended (See four byte instruction formats in Table 27-16

Power-up sequence:

Apply power between V

CC and GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to “0”.

Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

The serial programming instructions will not work if the communication is out of synchro-

nization. When in sync. the second byte (0x53), will echo back when issuing the third

byte of the Programming Enable instruction. Whether the echo is correct or not, all four

bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a

positive pulse and issue a new Programming Enable command.

The Flash is programmed one page at a time. The page size is found in Table 27-7 on

page 298. The memory page is loaded one byte at a time by supplying the 6 LSB of the

address and data together with the Load Program Memory Page instruction. To ensure

correct loading of the page, the data low byte must be loaded before data high byte is

VCC

GND

XTAL1

SCK

MISO

MOSI

RESET

+1.8 - 5.5V

AVCC

+1.8 - 5.5V

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