ATmega169P datasheet(206/393 Pages) ATMEL

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8018N–AVR–08/09

ATmega169P

20.2.5

Start Condition Detector

The start condition detector is shown in Figure 20-6. The SDA line is delayed (in the range of 50

to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled

in Two-wire mode.

The start condition detector is working asynchronously and can therefore wake up the processor

from the Power-down sleep mode. However, the protocol used might have restrictions on the

SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time set by

the CKSEL Fuses (see ”Clock Systems and their Distribution” on page 30) must also be taken

into the consideration. Refer to the USISIF bit description on page 207 for further details.

20.2.6

Clock speed considerations.

Maximum frequency for SCL and SCK is f_CK /4. This is also the maximum data transmit and

receieve rate in both two- and three-wire mode. In two-wire slave mode the Two-wire Clock Con-

trol Unit will hold the SCL low until the slave is ready to receive more data. This may reduce the

actual data rate in two-wire mode.

20.3

Alternative USI Usage

When the USI unit is not used for serial communication, it can be set up to do alternative tasks

due to its flexible design.

20.3.1

Half-duplex Asynchronous Data Transfer

By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact

and higher performance UART than by software only.

20.3.2

4-bit Counter

The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the

counter is clocked externally, both clock edges will generate an increment.

20.3.3

12-bit Timer/Counter

Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit

counter.

20.3.4

Edge Triggered External Interrupt

By setting the counter to maximum value (F) it can function as an additional external interrupt.

The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature

is selected by the USICS1 bit.

20.3.5

Software Interrupt

The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.

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