ATmega169P datasheet(185/393 Pages) ATMEL

185 / 393 page

185

8018N–AVR–08/09

ATmega169P

19.8

Asynchronous Data Reception

The USART includes a clock recovery and a data recovery unit for handling asynchronous data

reception. The clock recovery logic is used for synchronizing the internally generated baud rate

clock to the incoming asynchronous serial frames at the RxD pin. The data recovery logic sam-

ples and low pass filters each incoming bit, thereby improving the noise immunity of the

Receiver. The asynchronous reception operational range depends on the accuracy of the inter-

nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits.

19.8.1

Asynchronous Clock Recovery

The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 19-5

on page 185 illustrates the sampling process of the start bit of an incoming frame. The sample

rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed

mode. The horizontal arrows illustrate the synchronization variation due to the sampling pro-

cess. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of

operation. Samples denoted zero are samples done when the RxD line is idle (i.e., no communi-

cation activity).

Figure 19-5. Start Bit Sampling

When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the

start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in

the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-

ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the

figure), to decide if a valid start bit is received. If two or more of these three samples have logical

high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts

looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-

ery logic is synchronized and the data recovery can begin. The synchronization process is

repeated for each start bit.

19.8.2

Asynchronous Data Recovery

When the receiver clock is synchronized to the start bit, the data recovery can begin. The data

recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight

states for each bit in Double Speed mode. Figure 19-6 on page 186 shows the sampling of the

data bits and the parity bit. Each of the samples is given a number that is equal to the state of

the recovery unit.

START

IDLE

BIT 0

123

678

RxD

Sample

(U2X = 0)

Sample

(U2X = 1)

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