ATmega169P datasheet(151/393 Pages) ATMEL

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151

8018N–AVR–08/09

ATmega169P

from Power-down or Standby mode due to unstable clock signal upon start-up, no matter

whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.

• Description of wake up from Power-save or ADC Noise Reduction mode when the timer is

clocked asynchronously: When the interrupt condition is met, the wake up process is started

on the following cycle of the timer clock, that is, the timer is always advanced by at least one

before the processor can read the counter value. After wake-up, the MCU is halted for four

cycles, it executes the interrupt routine, and resumes execution from the instruction following

SLEEP.

• Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect

result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be

done through a register synchronized to the internal I/O clock domain. Synchronization takes

place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock

(clk

I/O) again becomes active, TCNT2 will read as the previous value (before entering sleep)

until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-

save mode is essentially unpredictable, as it depends on the wake-up time. The recommended

procedure for reading TCNT2 is thus as follows:

Write any value to either of the registers OCR2A or TCCR2A.

Wait for the corresponding Update Busy Flag to be cleared.

Read TCNT2.

• During asynchronous operation, the synchronization of the Interrupt Flags for the

asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore

advanced by at least one before the processor can read the timer value causing the setting of

the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not

synchronized to the processor clock.

ATmega169P датащи(PDF) 151 Page - ATMEL Corporation