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AT89LP428 датащи(PDF) 136 Page - ATMEL Corporation |
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AT89LP428 датащи(HTML) 136 Page - ATMEL Corporation |
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136 / 149 page ![]() 136 3654A–MICRO–8/09 AT89LP428/828 Figure 24-15. Shift Register Mode Timing Waveform 24.9 Test Conditions 24.9.1 AC Testing Input/Output Waveform(1) Note: 1. AC Inputs during testing are driven at V CC - 0.5V for a logic “1” and 0.45V for a logic “0”. Timing measurements are made at VIH min. for a logic “1” and VIL max. for a logic “0”. 24.9.2 Float Waveform(1) Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded VOH/VOL level occurs. 24.8 Serial Port Timing: Shift Register Mode The values in this table are valid for V CC = 2.4V to 5.5V and Load Capacitance = 80 pF. Symbol Parameter Variable Oscillator Units Min Max tXLXL Serial Port Clock Cycle Time 2tCLCL -15 µs t QVXH Output Data Setup to Clock Rising Edge t CLCL -15 ns tXHQX Output Data Hold after Clock Rising Edge tCLCL -15 ns tXHDX Input Data Hold after Clock Rising Edge 0 ns t XHDV Input Data Valid to Clock Rising Edge 15 ns 01 2 3 4 5 6 7 Valid Valid Valid Valid Valid Valid Valid Valid Clock Write to SBUF Output Data Clear RI Input Data |
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