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AT89LP428 датащи(PDF) 126 Page - ATMEL Corporation |
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AT89LP428 датащи(HTML) 126 Page - ATMEL Corporation |
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126 / 149 page ![]() 126 3654A–MICRO–8/09 AT89LP428/828 23.9.6 Timing Parameters The timing parameters for Figure 23-5, Figure 23-6, Figure 23-7, Figure 23-8, and Figure 23-10 are shown in Table 23-8. Note: 1. t SCK is independent of tCLCL. Table 23-8. Programming Interface Timing Parameters Symbol Parameter Min Max Units t CLCL System Clock Cycle Time 0 60 ns tPWRUP Power On to SS High Time 10 µs tPOR Power-on Reset Time 100 µs t PWRDN SS Tristate to Power Off 1 µs tRLZ RST Low to I/O Tristate tCLCL 2 tCLCL ns tSTL RST Low Settling Time 100 ns t RHZ RST High to SS Tristate 0 2 t CLCL ns tSCK Serial Clock Cycle Time 200(1) ns tSHSL Clock High Time 75 ns t SLSH Clock Low Time 50 ns tSR Rise Time 25 ns tSF Fall Time 25 ns t SIS Serial Input Setup Time 10 ns tSIH Serial Input Hold Time 10 ns t SOH Serial Output Hold Time 10 ns t SOV Serial Output Valid Time 35 ns tSOE Output Enable Time 10 ns t SOX Output Disable Time 25 ns t SSE SS Enable Lead Time t SLSH ns tSSD SS Disable Lag Time tSLSH ns t ZSS SCK Setup to SS Low 25 ns t SSZ SCK Hold after SS High 25 ns tWR Write Cycle Time 2.5 ms t AWR Write Cycle with Auto-Erase Time 5 ms t ERS Chip Erase Cycle Time 7.5 ms |
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