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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATmega165 датащи(PDF) 137 Page - ATMEL Corporation |
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ATmega165 датащи(HTML) 137 Page - ATMEL Corporation |
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137 / 336 page  137 ATmega165/V 2573G–AVR–07/09 Timer/Counter2 Interrupt Flag Register – TIFR2 • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. • Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. Bit 7654 321 0 – – – – – – OCF2A TOV2 TIFR2 Read/Write R RRRR R R/W R/W Initial Value 0000 000 0 |
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