ATmega165 datasheet(44/336 Pages) ATMEL

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ATmega165/V

2573G–AVR–07/09

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is

written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared

if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the follow-

ing procedure must be followed:

In the same operation, write a logic one to WDCE and WDE. A logic one must be

written to WDE even though it is set to one before the disable operation starts.

Within the next four clock cycles, write a logic 0 to WDE. This disables the

Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algo-

rithm described above. See “Timed Sequences for Changing the Configuration of the

Watchdog Timer” on page 45.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0

The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the

Watchdog Timer is enabled. The different prescaling values and their corresponding

Timeout Periods are shown in Table 21.

Note:Also see Figure 183 on page 312.

Table 21. Watchdog Timer Prescale Select

WDP2

WDP1

WDP0

Number of WDT

Oscillator Cycles

Typical Time-out

at VCC = 3.0V

Typical Time-out

at VCC = 5.0V

16K cycles

15.4 ms

14.7 ms

32K cycles

30.8 ms

29.3 ms

64K cycles

61.6 ms

58.7 ms

128K cycles

0.12 s

256K cycles

0.25 s

0.23 s

512K cycles

0.49 s

0.47 s

1,024K cycles

1.0 s

0.9 s

2,048K cycles

2.0 s

1.9 s

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