ATmega165 datasheet(140/336 Pages) ATMEL

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140

ATmega165/V

2573G–AVR–07/09

each data packet, the Master will synchronize the Slave by pulling high the Slave Select,

SS, line.

When configured as a Master, the SPI interface has no automatic control of the SS line.

This must be handled by user software before communication can start. When this is

done, writing a byte to the SPI Data Register starts the SPI clock generator, and the

hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock gener-

ator stops, setting the end of Transmission Flag (SPIF). If the SPI Interrupt Enable bit

(SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue

to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high

the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for

later use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated

as long as the SS pin is driven high. In this state, software may update the contents of

the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock

pulses on the SCK pin until the SS pin is driven low. As one byte has been completely

shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE,

in the SPCR Register is set, an interrupt is requested. The Slave may continue to place

new data to be sent into SPDR before reading the incoming data. The last incoming byte

will be kept in the Buffer Register for later use.

Figure 66. SPI Master-slave Interconnection

The system is single buffered in the transmit direction and double buffered in the receive

direction. This means that bytes to be transmitted cannot be written to the SPI Data

received character must be read from the SPI Data Register before the next character

has been completely shifted in. Otherwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To

ensure correct sampling of the clock signal, the minimum low and high periods should

be:

Low period: Longer than 2 CPU clock cycles.

High period. Longer tha 2 CPU clock cycles.

SHIFT

ENABLE

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