ATmega165 datasheet(90/336 Pages) ATMEL

90 / 336 page

ATmega165/V

2573G–AVR–07/09

the edge detector uses sampling, the maximum frequency of an external clock it can

detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari-

ation of the system clock frequency and duty cycle caused by Oscillator source (crystal,

resonator, and capacitors) tolerances, it is recommended that maximum frequency of an

external clock source is less than f

clk_I/O/2.5.

An external clock source can not be prescaled.

Figure 39. Prescaler for Timer/Counter0 and Timer/Counter1

(1)

Note:

1. The synchronization logic on the input pins (

T1/T0) is shown in Figure 38.

General Timer/Counter

Control Register – GTCCR

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this

mode, the value that is written to the PSR2 and PSR10 bits is kept, hence keeping the

corresponding prescaler reset signals asserted. This ensures that the corresponding

Timer/Counters are halted and can be configured to the same value without the risk of

one of them advancing during configuration. When the TSM bit is written to zero, the

PSR2 and PSR10 bits are cleared by hardware, and the Timer/Counters start counting

simultaneously.

• Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This

bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that

Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this pres-

caler will affect both timers.

PSR10

Clear

clk

I/O

Synchronization

Bit

TSM

–

PSR2

PSR10

GTCCR

Read/Write

R/W

Initial Value

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