ATmega165 datasheet(118/336 Pages) ATMEL

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118

ATmega165/V

2573G–AVR–07/09

Input Capture Register 1 –

ICR1H and ICR1L

The Input Capture is updated with the counter (TCNT1) value each time an event occurs

on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1).

The Input Capture can be used for defining the counter TOP value.

The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes

are read simultaneously when the CPU accesses these registers, the access is per-

formed using an 8-bit temporary High Byte Register (TEMP). This temporary register is

shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 94.

Timer/Counter1 Interrupt

Mask Register – TIMSK1

• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glob-

ally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 46.) is executed when the ICF1 Flag, located

in TIFR1, is set.

• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glob-

ally enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 46.) is executed when the

OCF1B Flag, located in TIFR1, is set.

• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glob-

ally enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The

corresponding Interrupt Vector (See “Interrupts” on page 46.) is executed when the

OCF1A Flag, located in TIFR1, is set.

• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts glob-

ally enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding

Interrupt Vector (See “Interrupts” on page 46.) is executed when the TOV1 Flag, located

in TIFR1, is set.

Bit

7654

321

ICR1[15:8]

ICR1H

ICR1[7:0]

ICR1L

Read/Write

R/W

Initial Value

0000

000

Bit

7654

–

–ICIE1

–

OCIE1B

OCIE1A

TOIE1

TIMSK1

Read/Write

R/W

Initial Value

0000

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