IMX35 datasheet(63/148 Pages) FREESCALE

63 / 148 page

i.MX35 Applications Processors for Automotive Products, Rev. 6

Freescale Semiconductor

Figure 39. eSDHCv2 Timing

Table 44. eSDHCv2 Interface Timing Specification

Parameter

Symbols Min. Max.

Unit

Card Input Clock

SD1 Clock frequency (Low Speed)

fPP

1 In low-speed mode, the card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

400

kHz

Clock frequency (SD/SDIO Full Speed/High Speed)

fPP

2 In normal-speed mode for the SD/SDIO card, clock frequency can be any value between 0–25 MHz. In high-speed mode,

clock frequency can be any value between 0–50 MHz.

025/50 MHz

Clock frequency (MMC Full Speed/High Speed)

fPP

3 In normal-speed mode for MMC card, clock frequency can be any value between 0 and 20 MHz. In high-speed mode, clock

frequency can be any value between 0–52 MHz.

020/52 MHz

Clock frequency (Identification Mode)

fOD

100

400

kHz

SD2 Clock Low time

tWL

7—

SD3 Clock high time

tWH

7—

SD4 Clock rise time

tTLH

—3

SD5 Clock fall time

tTHL

—3

eSDHC Output/Card Inputs CMD, DAT (Reference to CLK)

SD6 eSDHC output delay

tOD

–3

eSDHC Input/Card Outputs CMD, DAT (Reference to CLK)

SD7 eSDHC input setup time

tISU

5—

SD8 eSDHC input hold time

tIH

4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

2.5

—

SD1

SD3

SD5

SD4

SD7

SDHCx_CMD

output from eSDHCv2 to card

SDHCx_DAT_1

SDHCx_DAT_7

SDHCx_DAT_0

output from card to eSDHCv2

SDHCx_CLK

SD2

SD8

SD6

SDHCx_CMD

SDHCx_DAT_1

SDHCx_DAT_7

SDHCx_DAT_0

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