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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HC05 датащи(PDF) 22 Page - Motorola, Inc |
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HC05 датащи(HTML) 22 Page - Motorola, Inc |
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22 / 232 page  MOTOROLA 1-2 MC68HC05X16 Rev. 1 INTRODUCTION 1 1.1 Features Hardware features • Fully static design featuring the industry standard M68HC05 family CPU core • On chip crystal oscillator with divide-by -2, -4, -8 or -10, or a software selectable divide-by -32, -64, -128 or -160 option (SLOW mode) • 352 bytes of RAM • 15102 bytes of user ROM plus 16 bytes of user vectors • 256 bytes of byte erasable EEPROM with internal charge pump and security bit • Write/erase protect bit for 224 of the 256 bytes EEPROM • Bootstrap firmware • Power saving STOP, WAIT and SLOW modes • Three 8-bit parallel I/O ports and one 8-bit input-only port; wired-OR interrupt capability on all port B pins • Motorola controller area network (MCAN) with line interface circuitry • Software option available to output the internal E-clock to port pin PC2 • 16-bit timer with 2 input captures and 2 output compares • Computer operating properly (COP) watchdog timer • Serial communications interface system (SCI) with independent transmitter/receiver baud rate selection; receiver wake-up function for use in multi-receiver systems • 8 channel A/D converter • 2 pulse length modulation systems which can be used as D/A converters • One interrupt request input plus 4 on-board hardware interrupt sources • 2.2 MHz bus speed • –40 to +125 °C temperature range • Available in 64-pin quad flat pack (QFP) package • Complete development system support available using the MMDS05 or M68MMPFB0508 development station with the M68EML05X32 emulation module or the M68HC05XEVS evaluation system 20 |
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