HC05 datasheet(13/232 Pages) MOTOROLA

13 / 232 page

MC68HC05X16

Rev. 1

MOTOROLA

TABLE OF CONTENTS

Paragraph

Number

Page

Number

TITLE

ANALOG TO DIGITAL CONVERTER

9.1

A/D converter operation......................................................................................... 9-1

9.2

A/D registers.......................................................................................................... 9-3

9.2.1

Port D data register (PORTD).......................................................................... 9-3

9.2.2

A/D result data register (ADDATA) ................................................................... 9-3

9.2.3

A/D status/control register (ADSTAT)............................................................... 9-4

9.3

A/D converter during STOP mode ......................................................................... 9-5

9.4

A/D converter during WAIT mode.......................................................................... 9-6

9.5

Port D analog input................................................................................................ 9-6

RESETS AND INTERRUPTS

10.1

Resets ................................................................................................................. 10-1

10.1.1

Power-on reset............................................................................................... 10-2

10.1.2

Miscellaneous register .................................................................................. 10-2

10.1.3

RESET pin ..................................................................................................... 10-3

10.1.4

Computer operating properly (COP) watchdog reset .................................... 10-3

10.1.4.1

COP watchdog during STOP mode ......................................................... 10-5

10.1.4.2

COP watchdog during WAIT mode .......................................................... 10-5

10.1.5

Functions affected by reset............................................................................ 10-5

10.2

Interrupts ............................................................................................................. 10-7

10.2.1

Interrupt priorities........................................................................................... 10-9

10.2.2

Nonmaskable software interrupt (SWI) .......................................................... 10-9

10.2.3

Maskable hardware interrupts........................................................................ 10-9

10.2.3.1

Miscellaneous register ............................................................................. 10-10

10.2.3.2

External interrupts.................................................................................... 10-11

10.2.3.3

MCAN interrupt (CIRQ) ............................................................................ 10-11

10.2.3.4

Timer interrupts ........................................................................................ 10-12

10.2.3.5

Serial communications interface (SCI) interrupts..................................... 10-12

10.2.4

Hardware controlled interrupt sequence ........................................................ 10-13

CPU CORE AND INSTRUCTION SET

11.1

Registers ............................................................................................................. 11-1

11.1.1

Accumulator (A) ............................................................................................. 11-1

11.1.2

Index register (X) ........................................................................................... 11-2

11.1.3

Program counter (PC).................................................................................... 11-2

11.1.4

Stack pointer (SP).......................................................................................... 11-2

11.1.5

Condition code register (CCR)....................................................................... 11-2

11.2

Instruction set ...................................................................................................... 11-3

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