HC05 datasheet(68/232 Pages) MOTOROLA

68 / 232 page

MOTOROLA

5-6

MC68HC05X16

Rev. 1

MOTOROLA CAN MODULE (MCAN)

5.3.1

MCAN control register (CCNTRL)

This register may be read or written to by the MCU; only the RR bit is affected by the MCAN.

MODE — Undeﬁned mode

This bit must never be set by the CPU as this would result in the transmit and receive buffers being

mapped out of memory. The bit is cleared on reset, and should be left in this state for normal

operation.

SPD — Speed mode

1 (set)

–

Slow – Bus line transitions from both ‘recessive’ to ‘dominant’ and

from ‘dominant’ to ‘recessive’ will be used for resynchronization.

0 (clear) –

Fast – Only transitions from ‘recessive’ to ‘dominant’ will be used for

resynchronization.

OIE — Overrun interrupt enable

1 (set)

–

Enabled – The CPU will get an interrupt request whenever the

Overrun Status bit gets set.

0 (clear) –

Disabled – The CPU will get no overrun interrupt request.

EIE — Error interrupt enable

1 (set)

–

Enabled – The CPU will get an interrupt request whenever the error

status or bus status bits in the CSTAT register change.

0 (clear) –

Disabled – The CPU will get no error interrupt request.

TIE — Transmit interrupt enable

1 (set)

–

Enabled – The CPU will get an interrupt request whenever a

message has been successfully transmitted, or when the transmit

buffer is accessible again following an ABORT command.

0 (clear) –

Disabled – The CPU will get no transmit interrupt request.

Address

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

Reset

condition

State

on reset

MCAN control (CCNTRL)

$0020

MODE

SPD

OIE

EIE

TIE

RIE

External reset 0u - u uuu1

RR bit set

0u - u uuu1

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