STM32F101C6U6ATR datasheet(60/73 Pages) STMICROELECTRONICS

номер детали	STM32F101C6U6ATR

подробное описание детали	Low-density access line, ARM-based 32-bit MCU with 16 or 32 KB Flash, 5 timers, ADC and 4 communication interfaces

PDF	73 Pages

Scroll/Zoom	100%

производитель	STMICROELECTRONICS [STMicroelectronics]

домашняя страница	http://www.st.com

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60 / 73 page

Electrical characteristics

STM32F101x4, STM32F101x6

60/74

Doc ID 15058 Rev 3

5.3.16

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 41 are derived from tests

performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage

conditions summarized in Table 8.

Note:

It is recommended to perform a calibration after each power-up.

Table 41.

ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Power supply

2.4

3.6

fADC

ADC clock frequency

0.6

MHz

(1)

Sampling rate

0.05

MHz

fTRIG

(1)

External trigger frequency

fADC = 14 MHz

823

kHz

1/fADC

VAIN

Conversion voltage range(2)

0 (VSSA or VREF-

tied to ground)

VREF+

RAIN

(1)

External input impedance

See Equation 1 and

Table 42 for details



RADC

(1)

Sampling switch resistance



CADC

(1)

Internal sample and hold

capacitor

8pF

tCAL

(1)

Calibration time

fADC = 14 MHz

5.9

µs

1/fADC

tlat

(1)

Injection trigger conversion

latency

fADC = MHz

0.214

µs

3(3)

1/fADC

tlatr

(1)

Regular trigger conversion

latency

fADC = 14 MHz

0.143

µs

2(3)

1/fADC

(1)

Sampling time

fADC = 14 MHz

0.107

17.1

µs

1.5

239.5

1/fADC

tSTAB

(1)

Power-up time

µs

tCONV

(1)

Total conversion time

(including sampling time)

fADC = 14 MHz

µs

14 to 252 (tS for sampling +12.5 for

successive approximation)

1/fADC

Guaranteed by design, not tested in production.

VREF+ is internally connected to VDDA and VREF- is be internally connected to VSSA.

For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 41.

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