TMC2192 datasheet(31/69 Pages) CADEKA

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PRODUCT SPECIFICATION

TMC2192

REV. 1.0.0 8/13/03

Serial Control Port (R-Bus)

In addition to the 12-wire parallel port, a 2-wire serial con-

trol interface is provided, active when SER is LOW. Either

port alone can control the entire chip. Up to four TMC2192

devices may be connected to the 2-wire serial interface with

each device having a unique address.

The 2-wire interface comprises a clock (SCL) and a bi-direc-

tional data (SDA) pin. The encoder acts as a slave for receiv-

ing and transmitting data over the serial interface. When the

serial interface is not active, the logic levels on SCL and

SDA need to be pulled HIGH by external pull-up resistors.

Data received or transmitted on the SDA line must be stable

for the duration of the positive-going SCL pulse. Data on

SDA must change only when SCL is LOW. If SDA changes

state while SCL is HIGH, the serial interface interprets that

action as a start or stop sequence.

There are six components to serial bus operation:

• Start signal

• Slave address byte

• Block Pointer

• Offset Pointer

• Data byte to read or write

• Stop signal

When the serial interface is inactive (SCL and SDA are

HIGH) communications are initiated by sending a start sig-

nal. The start signal is a HIGH-to-LOW transition on SDA

while SCL is HIGH. This signal alerts all slaved devices that

a data transfer sequence is coming.

The ﬁrst eight bits of data transferred after a start signal com-

prise a seven bit slave address and a single R/W bit. The R/W

bit indicates the direction of data transfer, read from or write

to the slave device. If the transmitted slave address matches

the address of the device (set by the state of the SA1-0 input

pins in Table 24), the TMC2192 acknowledges by bringing

SDA LOW on the 9th SCL pulse. If the addresses do not

match, the TMC2192 will not acknowledge.

Data Transfer via Serial Interface

For each byte of data read or written, the MSB is the ﬁrst bit

of the sequence.

If the TMC2192 does not acknowledge the master device

during a write sequence, the SDA remains HIGH so the mas-

ter can generate a stop signal. If the master device does not

acknowledge the TMC2192 during a read sequence, the

encoder interprets this as “end of data”.

Writing data to speciﬁc control registers of the TMC2192

requires that the 8 bit address of the control register of inter-

est be written after the slave address has been established.

This control register address is the base address for subse-

quent write operations. The base address auto increments by

one for each byte of data written after the data byte intended

for the base address.

Figure 25. Serial Port Read/Write Timing

Data are read from the control registers of the TMC2192 in a

similar manner. Reading requires two data transfer opera-

tions:

The base address must be written with the R/W bit of the

slave address byte LOW to set up a sequential read opera-

tion.

Reading (the R/W bit of the slave address byte HIGH)

begins at the previously established base address. The

address of the read register auto increments after each byte is

transferred.

To terminate a write sequence to the TMC2192, a stop signal

must be sent. A stop signal comprises a LOW-to-HIGH tran-

sition of SDA while SCL is HIGH. To terminate a read

Table 21. Serial Port Addresses

(SA1)

(SA0)

1010100

1010101

1010110

1010111

tBUFF

tSTAH

tSTASU

tSTOSU

tDHO

tDSU

tDAL

tBAH

SCL / CS

SDA / R/W

65-6294-28

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